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What is a Master-Slave J-K Flip Flop

Written by Harpreet

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The problem of race around condition in a J-K flip flop when both the inputs to it are'1' can be solved by using a Master Slave configuration. The following are the constructional features of a Master-Slave J-K flip flop:-


It consists of two S-R flip flops connected in series with each other, so that the outputs of the first flip flop act as inputs to the second. The outputs of the second flip-flip say Q and Q', are fed back to the first flip flop along with the original inputs S and R by using two AND gates. The new inputs J and K thus obtained are given by the logical equations:-

J=S.Q' -- (1)

K= R.Q --- (2)

The same clock is fed to both the flip flops but an inverter gate is used in the line that carries the clock signal to the second flip flop.

A Master-Slave J-K flip works as an ordinary R-S flip flop for the input conditions of J=0 and K=0 (memory state), J=0 and K=1 (reset state), J=1 and K=0 (set state). For the inputs J=1 and K=1 which is an unused and unreliable state in an ordinary R-S flip flop, but due to the feedback of the outputs in to the inputs as shown by equations (1) and (2), this state now acts as a toggle state of a flip flop. This means that whenever J=1 and K=1 are the inputs to the flip flop, the outputs Q and Q’ both get complimented from their previous values.

If a Master-slave configuration is not used, then this toggle state can’t be achieved because the outputs being fed back will continue to the affect the inputs throughout the whole of the clock period and thus would keep on complimenting themselves until the clock turns low. This is known as a race around condition which can’t be used in any practical systems.

To make sure that the outputs of the flip flop toggle only once throughout the whole of the clock period, a Master-Slave configuration is used. The key in this configuration is the clock signal that is fed to the second flip flop through an inverter gate. Thus when the clock is high, inputs are fed in to the first flop and its outputs are determined. But these outputs are only passed on to the second flip flop when the clock turns low because of the presence of the inverter gate. Now the outputs of the second flip flop change but can’t affect the inputs of the first flop because of the fact that the clock to the first flip flop is now low. Therefore a Master Slave configuration makes sure that the outputs only change once in a clock cycle.

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